The date of registration : 2010.07.28
| First Name | **** | Last Name | **** |
|---|---|---|---|
| Gender | **** | Date of Birth | **** |
| **** | Nationality | Singapore | |
| Street Address | **** | ||
| City | Singapore | Country | Singapore |
| Objective | Electronic Designer | ||
| Salary Expectation | (USD) 0 / year | ||
| Primary Contact Number |
****-**** | Secondary Contact Number | ****-**** |
|---|---|---|---|
| Field Desired | Electronics Engineers, Except Computer | ||
| Keyword Search | Analog/Mixed-signal IC Design,Electronics Design | ||
| Preferred Location | 1st : None | 2nd : | 3rd : |
| Languages Spoken | English(Native) | Chinese( Fluent) | |
| From - To (mm/yyyy) |
Employer | Position | ||
|---|---|---|---|---|
07.2009 ~ 07.2010 |
Company Name | EDB Training Program | Title | Trainee |
| Categories | Electronics Engineers, Except Computer | |||
| Country | Singapore | |||
| Reason For Leaving | ||||
| Detailed Explanation | 1. Verifications of digital macrocells in an embedded secure microcontroller SOC. The digital macrocells verified are:- RAM-interface, Timer, CRC module, Encryption module and Secure modules.
2. Spyglass verification of RTL coding style, clock-domains-crossing (CDC), asynchronous reset, clock synchronization and DFT. 3. ICCR verification of code coverage of RTL expressions, blocks/branches and toggle. 4. PSL/ABV verification for assertion based verifications embedded in simulations for early fault detection, but non-silicon tests. 5. Certitude qualification of verification environment and debug of inactivated, un-propagated and un-detected faults. 6. Verifications of encryption/scrambling modules for RAM with Firewall registers. 7. Verifications of secure modules for protecting registers and flagging alarm in the event of secure violations. High security in hardware is required for all Smartcard applications. 8. Top-level regression at chip-level for the secure CPU and its connected macrocells. 9. Documentations (using Framemaker) of design specifications and verification specifications, with version control. 10. Setup of project environment in Clearcase. Setup of tools environment which includes evaluating verification tools such as Certitude and Verdi. 11. Debugging of C/ASM test patterns that are loaded into RAM/ROM and simulated at chip-level. |
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01.2008 ~ 03.2009 |
Company Name | Xilinx | Title | Senior IC Designer |
| Categories | Electronics Engineers, Except Computer | |||
| Country | Singapore | |||
| Reason For Leaving | ||||
| Detailed Explanation | 1. Verifications of the performance and functionality of FPGA blocks in nanometer CMOS technology. The custom blocks verified are: Configurable Logic Blocks (CLB), Look-Up-Tables, Shift-registers, Memory-Cells, Configuration Data-Registers, Global buffers. The methodologies are based on: Negative-bias Temperature Instability (NBTI) and Single Event Upset (SEU) analysis. The main tool used is HSIM-MOSRA, which is an accurate tool used to extrapolate IC reliability.
2. FPGA derivative consisting of a sub-system glued with programmable-logic requires the transistor-level design of level-shifters as an interface between dual power-supplies systems. |
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06.2006 ~ 12.2007 |
Company Name | International Rectifier | Title | Senior Analog Designer |
| Categories | Electronics Engineers, Except Computer | |||
| Country | Singapore | |||
| Reason For Leaving | ||||
| Detailed Explanation | A senior analog designer individually responsible for designing ultra-high-voltage IC chip for power-supplies and motor-drive applications. In the development of the ICs, a couple of inventions are filed and one is patented (US 2008/0211476). The ICs designed from application datasheets are:-
1. Universal Active Oring in 600V 1um technology. The IC features patented HV signal-input\'s protection, as well as patented HV power-supply shunt-regulation. 2. PDP ramp-driver in 600V 1um technology, with additional generic high-side driver. The PDP ramp driver operates in linear-ramp, exponential-ramp and liner-steps modes. 3. Three-phase motor driver in 600V 1um technology. The IC features independent GND pins for the low-side drivers with an immunity of �5V from signal-input\'s GND. 4. Patented high-voltage auxiliary start-up circuit and layout-architecture. The circuit features patented high-voltage device layout architecture suitable for the auxiliary start-up circuit. The auxiliary circuit is built around a patented method of boot-strap diode emulator circuit. |
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01.2005 ~ 05.2006 |
Company Name | O2micro | Title | Senior Analog Designer |
| Categories | Electronics Engineers, Except Computer | |||
| Country | Singapore | |||
| Reason For Leaving | ||||
| Detailed Explanation | A senior analog designer working in a team that is responsible for designing power-supplies full-IC-chip for batteries management. The ICs designed from application datasheets are:-
1. Seven-cell Lithium-ion battery pack control IC for power-tools and hybrid-vehicles. The IC, fabricated in 0.35um 5V/40V technology, features built-in cell balancing and a sigma-delta converter used for individual cell voltage, battery current, internal or external temperature measurements. The SD converter has a resolution and speed of, and selects the measuring channel using multi-input software programmable multiplexer. 2. Single battery charger and selector IC in 0.35um 5V/40V technology. The IC features a NMOS synchronous buck converter that supports fast charge current and high-accuracy constant voltage operations. The IC also features a “keep-alive” circuitry for boosting the charge on the external bootstrap-capacitor such as to allow maximum duty-cycle. |
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07.2000 ~ 12.2004 |
Company Name | Infineon Technologies Asia Pacific | Title | Analog Designer |
| Categories | Electronics Engineers, Except Computer | |||
| Country | Singapore | |||
| Reason For Leaving | ||||
| Detailed Explanation | An analog designer working in a team that is responsible for designing analog/mixed-signal modules for SOC in telecommunications and network applications. The modules designed are:-
1. Analog Front-End (AFE) codec for Voice-over-IP applications in 0.18um/3.3V and 0.12um/2.5V technology. The AFE consist of a transmit path from the microphone and receive path to the loudspeaker. The transmit/receive paths consist of sigma-delta ADC/DAC, Pre-filters/post-filters, variable gain-amplifiers for volume-control, low-impedance output drivers and low-noise input amplifiers. 2. Temperature sensing module in 0.12um/2.5V technology. The module features a current-mode, wide-range (-50C to 150C) temperature-sensing core and a fully-differential, current-mode, discrete-time, sigma-delta ADC. The output of the high-resolution, 10-bit ADC goes through a customized digital-processing shell to give an 8-bit temperature code. 3. Linear Voltage Regulator in 0.18um/3.3V technology. The regulator has a driving capability of 75mA and regulates the output voltage of 1.8V from a supply voltage of 3.3V. 4. Process tracking/monitoring ADC-resistor module in 0.18um/3.3V technology. The module features a “process-tracking” ADC whose output is used as digital correction to RC filters and the current-references. 5. Switch in Ethernet PHY for Power-Over-LAN (POL) applications in 0.18um/3.3V. The switch is a special silicon device specifically tailored in its layout architecture. 6. Fuse-bank circuitry for software fusing in 0.18um/3.3V technology. The fuse-bank features a memory-cell method of soft fusing (reversible) for confirmation of trimming prior to hard fusing (permanent). 7. Power-supply start-up and shut-down sequencing module in 0.18um/3.3V technology. The module features customized start-up and shutdown sequencing control for under-voltage-lock-up (UVLOs) in multi-power-supplies ICs. 8. ISDN line-drivers and equalizers in 0.35um/3.3V technology. The ISDN drivers have driving capabilities of ~1 km of telephone wire. 9. Preliminary studies in LVDS (Low Voltage Differential Signaling). The LVDS transmitter features a differential, current-steering driver that transmits each signal across a dual-wire at speed of 650 Mbps. 10.Preliminary studies of Handset Detection in telephones. The detector features magnetic-signal coupling and echo-cancellation techniques. The detector is developed as an add-on to the voice-band AFE. |
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| School Name | Graduation Date (mm/yyyy) |
Continent/Country | Major | Degree |
|---|---|---|---|---|
| Nanyang Technological University | 07.1998 | SINGAPORE | Electricity & Electronics | B.S/B.A |
| Nanyang Technological University | 07.2000 | SINGAPORE | Electricity & Electronics | M.A |
| Technical Skills | Certificate Of Qualification | Level | Date |
|---|
| Special Skills Or Training |
1. Analog and Custom Design Tools Proficiency
- Cadence Design Environment, both frontend & backend: - Virtueso Layout, Schematic Composer, Spectre simulator, Assura/Diva Layout Verification - HSPICE and other spice-like simulators - HSIM and other fast-spice simulators - Matlab-Simulink and other system simulators - Orcad, Tanner L-edit. - Digital (RTL) Design and Verification Tools Proficiency - ClearCase Data Management in Unix/Linux - Unix scripting : gmake, csh, tcl, awk, perl - Spyglass RTL/CDC/netlist checks - ICCR Code Coverage (Block, Expression, Toggle) - Certitude VE (verification environment) qualification - NCSIM, NCVHDL for simulation and compilation of VHDL(RTL) and Verilog(netlist) - C/C++/ASM simulations for test patterns - Synthesis with DesignCompiler - Encounter SOC backend P&R PATENT & PUBLICATIONS 1. Patent Application Publication US 2008/0211476 A1: “High Voltage Shunt-regulator circuit with voltage-dependent resistor”. Inventor: Melvin Chow, Assignee: International Rectifier. 2. “High Resolution Sigma-Delta A/D Converter”, Master of Engineering Thesis, Nanyang Technological University, Melvin Chow. July 2001. Singapore 3. “Overloading in Multi-stage Sigma Delta Modulators” IEEE 1st Asia-Pacific Conference on ASICs, Melvin Chow. August 99. Seoul. 4. “A 14+bit Analog Frontend for wideband Voice Codecs” IEEE 10th International Symposium on Integrated Circuits, Devices & Systems. Yu Wen, Ma Fan Yung, Melvin Chow and Kenneth Choong. September 2004. Singapore. |
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| Cover Letter | |
| Expiration Date | 2011.12.31 |